Trend Analysis of the Costing of Denim Wash: A Study on Bangladeshi Washing Industries

Denim industry is one of the largest in the global market due to its exotic fashion trend. Bangladesh is the largest exporter of denim products over the European market and just after China in worldwide production. Fashion sense in denim fabric is drastically increasing due to the introduction of multiple washing methods. It is a type of fabric finishing treated in a different way for the change of appearance. This paper focuses on the denim washing cost trend within the year 2010 to 2018, and it aims to find out various consequences to analyze the market status of denim washing. The study uses the primary data collected from ten leading denim washing factories in Bangladesh. The study shows that, around 2010, the trend of dry washing processes was not so familiar. Hence, around 2015, there was an extensive practice executed which dominates the conventional wet washing technologies. On the contrary, process like sandblasting got banned from around 2013 because of its harmful effects on workers and users. Besides, various expensive wet washing technologies like acid wash, stone enzyme wash, towel wash, brightener treatment, optical wash, etc. has been incorporated to provide quality washing effects. This paper shows the costing trend of different wash technologies. This is because the majority of the dry and wet wash technologies became more expensive with time gradually due to the increase in labor cost, utility costs, chemical, and process costs. Furthermore, it also shows that some new technologies, like laser technology, which provided effective cost with reasonable quality through the initial investments, are high. The paper gives a prediction for the upcoming trend of denim washing as well as the cost of the technologies

A Logic Simplification Approach for Very Large Scale Crosstalk Circuit Designs

Crosstalk computing, involving engineered interference between nanoscale metal lines, offers a fresh perspective to scaling through co-existence with CMOS. Through capacitive manipulations and innovative circuit style, not only primitive gates can be implemented, but custom logic cells such as an Adder, Subtractor can be implemented with huge gains. Our simulations show over 5x density and 2x power benefits over CMOS custom designs at 16nm [1]. This paper introduces the Crosstalk circuit style and a key method for large-scale circuit synthesis utilizing existing EDA tool flow. We propose to manipulate the CMOS synthesis flow by adding two extra steps: conversion of the gate-level netlist to Crosstalk implementation friendly netlist through logic simplification and Crosstalk gate mapping, and the inclusion of custom cell libraries for automated placement and layout. Our logic simplification approach first converts Cadence generated structured netlist to Boolean expressions and then uses the majority synthesis tool to obtain majority functions, which is further used to simplify functions for Crosstalk friendly implementations. We compare our approach of logic simplification to that of CMOS and majority logic-based approaches. Crosstalk circuits share some similarities to majority synthesis that are typically applied to Quantum Cellular Automata technology. However, our investigation shows that by closely following Crosstalk's core circuit styles, most benefits can be achieved. In the best case, our approach shows 36% density improvements over majority synthesis for MCNC benchmark

Challenges and solutions for large-scale integration of emerging technologies

Title from PDF of title page viewed June 15, 2021Dissertation advisor: Mostafizur RahmanVitaIncludes bibliographical references (pages 67-88)Thesis (Ph.D.)--School of Computing and Engineering and Department of Physics and Astronomy. University of Missouri--Kansas City, 2021The semiconductor revolution so far has been primarily driven by the ability to shrink devices and interconnects proportionally (Moore's law) while achieving incremental benefits. In sub-10nm nodes, device scaling reaches its fundamental limits, and the interconnect bottleneck is dominating power and performance. As the traditional way of CMOS scaling comes to an end, it is essential to find an alternative to continue this progress. However, an alternative technology for general-purpose computing remains elusive; currently pursued research directions face adoption challenges in all aspects from materials, devices to architecture, thermal management, integration, and manufacturing. Crosstalk Computing, a novel emerging computing technique, addresses some of the challenges and proposes a new paradigm for circuit design, scaling, and security. However, like other emerging technologies, Crosstalk Computing also faces challenges like designing large-scale circuits using existing CAD tools, scalability, evaluation and benchmarking of large-scale designs, experimentation through commercial foundry processes to compete/co-exist with CMOS for digital logic implementations. This dissertation addresses these issues by providing a methodology for circuit synthesis customizing the existing EDA tool flow, evaluating and benchmarking against state-of-the-art CMOS for large-scale circuits designed at 7nm from MCNC benchmark suits. This research also presents a study on Crosstalk technology's scalability aspects and shows how the circuits' properties evolve from 180nm to 7nm technology nodes. Some significant results are for primitive Crosstalk gate, designed in 180nm, 65nm, 32nm, and 7nm technology nodes, the average reduction in power is 42.5%, and an average improvement in performance is 34.5% comparing to CMOS for all mentioned nodes. For benchmarking large-scale circuits designed at 7nm, there are 48%, 57%, and 10% improvements against CMOS designs in terms of density, power, and performance, respectively. An experimental demonstration of a proof-of-concept prototype chip for Crosstalk Computing at TSMC 65nm technology is also presented in this dissertation, showing the Crosstalk gates can be realized using the existing manufacturing process. Additionally, the dissertation also provides a fine-grained thermal management approach for emerging technologies like transistor-level 3-D integration (Monolithic 3-D, Skybridge, SN3D), which holds the most promise beyond 2-D CMOS technology. However, such 3-D architectures within small form factors increase hotspots and demand careful consideration of thermal management at all integration levels. This research proposes a new direction for fine-grained thermal management approach for transistor-level 3-D integrated circuits through the insertion of architected heat extraction features that can be part of circuit design, and an integrated methodology for thermal evaluation of 3-D circuits combining different simulation outcomes at advanced nodes, which can be integrated to traditional CAD flow. The results show that the proposed heat extraction features effectively reduce the temperature from a heated location. Thus, the dissertation provides a new perspective to overcome the challenges faced by emerging technologies where the device, circuit, connectivity, heat management, and manufacturing are addressed in an integrated manner.Introduction and motivation -- Cross talk computing overview -- Logic simplification approach for Crosstalk circuit design -- Crostalk computing scalability study: from 180 nm to 7 nm -- Designing large*scale circuits in Crosstalk at 7 nm -- Comparison and benchmarking -- Experimental demonstration of Crosstalk computing -- Thermal management challenges and mitigation techniques for transistor-level- 3D integratio

Thermal Management in Fine-Grained 3-D Integrated Circuits

For beyond 2-D CMOS logic, various 3-D integration approaches specially transistor based 3-D integrations such as monolithic 3-D [1], Skybridge [2], SN3D [3] holds most promise. However, such 3D architectures within small form factor increase hotspots and demand careful consideration of thermal management at all levels of integration [4] as stacked transistors are detached from the substrate (i.e., heat sink). Traditional system level approaches such as liquid cooling [5], heat spreader [6], etc. are inadequate for transistor level 3-D integration and have huge cost overhead [7]. In this paper, we investigate the thermal profile for transistor level 3-D integration approaches through finite element based modeling. Additionally, we propose generic physical level heat management features for such transistor level 3-D integration and show their application through detailed thermal modeling and simulations. These features include a thermal junction and heat conducting nano pillar. The heat junction is a specialized junction to extract heat from a selected region in 3-D; it allows heat conduction without interference with the electrical activities of the circuit. In conjunction with the junction, our proposed thermal pillars enable heat dissipation through the substrate; these pillars are analogous to TSVs/Vias, but carry only heat. Such structures are generic and is applicable to any transistor level 3-D integration approaches. We perform 3-D finite element based analysis to capture both static and transient thermal behaviors of 3-D circuits, and show the effectiveness of heat management features. Our simulation results show that without any heat extraction feature, temperature for 3-D integrated circuits increased by almost 100K-200K. However, proposed heat extraction feature is very effective in heat management, reducing temperature from heated area by up to 53%.Comment: 9 Page

A Light Weight Smartphone Based Human Activity Recognition System with High Accuracy

With the pervasive use of smartphones, which contain numerous sensors, data for modeling human activity is readily available. Human activity recognition is an important area of research because it can be used in context-aware applications. It has significant influence in many other research areas and applications including healthcare, assisted living, personal fitness, and entertainment. There has been a widespread use of machine learning techniques in wearable and smartphone based human activity recognition. Despite being an active area of research for more than a decade, most of the existing approaches require extensive computation to extract feature, train model, and recognize activities. This study presents a computationally efficient smartphone based human activity recognizer, based on dynamical systems and chaos theory. A reconstructed phase space is formed from the accelerometer sensor data using time-delay embedding. A single accelerometer axis is used to reduce memory and computational complexity. A Gaussian mixture model is learned on the reconstructed phase space. A maximum likelihood classifier uses the Gaussian mixture model to classify ten different human activities and a baseline. One public and one collected dataset were used to validate the proposed approach. Data was collected from ten subjects. The public dataset contains data from 30 subjects. Out-of-sample experimental results show that the proposed approach is able to recognize human activities from smartphones’ one-axis raw accelerometer sensor data. The proposed approach achieved 100% accuracy for individual models across all activities and datasets. The proposed research requires 3 to 7 times less amount of data than the existing approaches to classify activities. It also requires 3 to 4 times less amount of time to build reconstructed phase space compare to time and frequency domain features. A comparative evaluation is also presented to compare proposed approach with the state-of-the-art works

Sustainable technology readiness of apparel professionals in Bangladesh

Because of the increased awareness of sustainability and its impact on a company's performance and competitiveness, sustainability-related technology adoption has become an important topic in modern technology and business literature. The global apparel industry is one of the focal industries that consider sustainability a core element to protect the environment and ensure a better work environment for employees. Sustainable technologies can provide excellent opportunities for apparel firms to foster their operational performance and, at the same time, assist the firms in addressing sustainability requirements, especially in developing countries. It is imperative to investigate individual managers’ readiness toward sustainable technology. Previous studies paid little attention to the factors influencing apparel managers’ adoption of sustainable technology. Furthermore, existing literature has not addressed the factors impacting apparel managers’ sustainable technology readiness. Given the research gaps, this dissertation has three specific objectives: (1) to investigate the relationships between apparel managers’ knowledge and involvement in technology and their readiness toward sustainable technology; (2) to examine the moderating role of education and experience of the managers in the relationships between managers’ knowledge and involvement and their sustainable technology readiness; and (3) to investigate how apparel managers’ sustainable technology readiness, their perceptions of social influences, facilitating conditions, and relative advantage of sustainable technology impact their intention to adopt sustainable technology. To address the objectives, a conceptual model was developed based on a comprehensive literature review. The conceptual model is grounded on an integrated theoretical framework combining the unified theory of acceptance and use of technology (UTAUT), the diffusion of innovation theory (DOI), and the technology readiness index (TRI). A Qualtrics-designed online survey was used to collect data from Bangladeshi apparel managers to test the hypothesized relationships among latent constructs in the model. A total of 4315 surveys were distributed. 376 responses were received (8.71% response rate), and 221 valid responses were utilized for statistical analysis. The hypothesized relationships were tested using a two-step structural equation modeling. The measurement model was first evaluated using confirmatory factor analysis, and then the structural model was assessed to test the hypothesized relationships. The results of the hypotheses testing indicated significant relationships between apparel technology knowledge and sustainable technology readiness, between knowledge about the environmental impact of apparel production and sustainable technology readiness, and between social influences and adoption intention. The results did not support the hypothesized relationships between sustainable technology readiness and adoption intention or between facilitating conditions and adoption intention. The hypothesized relationship between personal involvement and sustainable technology readiness was not supported either. The moderating roles of education and experience were found insignificant in the relationships between knowledge and involvement and sustainable technology readiness. The dissertation provides several important contributions. First, the study focuses on sustainable technology readiness and adoption intention by apparel professionals, which previous researchers have not addressed. Second, this dissertation expands our understanding of the causal flow among cognitive variables of apparel managers, including their knowledge, personal involvement, technology readiness, and adoption intention toward sustainable technology. The study provides empirical evidence on the role of apparel professionals’ characteristics (e.g., knowledge and involvement) in their sustainable technology readiness. Third, the findings of this study provide valuable guidance for the government and other policymakers in increasing the use of sustainable technologies in the apparel industry. Utilizing the findings of this study, the government may develop strategies to support and train apparel managers to adopt sustainability related technologies. The apparel industry is the primary industry in Bangladesh. When the majority of apparel firms in Bangladesh start adopting sustainable technologies, it will be easier for Bangladesh to meet the Sustainable Development Goals (SDG), especially goal number 12 (Responsible Consumption and Production) and 13 (Climate Action)

New asymmetrical modular multilevel inverter topology with reduced number of switches

In this article, a new single-phase multilevel inverter is introduced with a reduced number of power switches and reduced voltage stress on power switches. The proposed topology consists of four input dc sources and nine semiconductor switches (eight unidirectional and one bidirectional switch). The topology can be used for asymmetrical voltage source configuration to generate seventeen voltage levels. The extended topology is constructed by a series connection of the topology circuit to produce higher voltage levels with less voltage stress on the switches without modifying the existing structure. Comparison is made with traditional and recently introduced topologies based on the number of power switches, dc sources, total blocking voltage of switches, and gate driver circuits, to prove the proposed topology's superiority. A simple nearest level modulation has been deployed as the switching scheme. Validation on the viability of the proposed topology has been carried out through simulation and hardware experimental setup